In memory designs, the read access time is the sum of delay times from three sources. These are the delays from address to row and column select, the delay from row select to a differential signal developing on the bitline, and the delay from the appearance of a signal differential on the bitlines to the output.
Referring to FIG. 1, there is depicted therein a single bitline column 100, having a plurality of cells, of which four, cells 101-104 are shown. Bitline 105, and its complement, bitline 106 are precharged by precharge circuit 107. During a precharge phase, precharge signal 108 is asserted, turning on p-type metal oxide semiconductor (PMOS) devices 109-111. PMOS devices 109 and 110 couple bitline 105 and bitline 106 to a voltage source. PMOS device 111 equalizes the charge on bitline 105 and bitline 106.
Precharge circuit 107 must precharge bitline capacitances 112 and 113 through bitline resistances 114 and 115. Bitline capacitances 112 and 113 represent the wire capacitances of the bitlines themselves as well as the capacitances associated with the memory cells on the bitline. These capacitances have been represented by lump capacitances 112 and 113, however, it would be understood that these capacitances are distributed along a length of bitline 105 and bitline 106, respectively. Similarly, resistances associated with bitline 105 and bitline 106 have been shown in FIG. 1 as lumped resistances 114 and 115, respectively, however, it would be understood that these resistances are distributed along the length of bitline 105 and bitline 106. The precharge time is determined by the "RC" time constant of the bitline resistances and the bitline capacitances.
During a read operation, data stored in one of memory cells 101-104 are transferred to the bitlines. Precharge signal 108 is negated, turning off PMOS devices 109-111 and precharge circuit 107, thereby decoupling bitline 105 and bitline 106 from the voltage source. Bitline 105 and bitline 106 are discharged to create a voltage differential across the bitlines. The voltage differential is transferred to the data lines, data 116 and data 117 through PMOS device 118 and PMOS device 119, respectively. During the read, PMOS devices 118 and 119 are turned on by asserting read select 120. The rate at which a differential is developed across bitline 105 and bitline 106, and consequently, data 116 and data 117 depends on the capacitances 112 and 113, and resistances 114 and 115, on the bitlines.
As memory increases in size, thereby increasing the number of cells on a bitline column, such as bitline column 100, bitline capacitance increases proportionately as bitline lengths increase to accommodate additional cells, as well as from added cell capacitance. Therefore, the read and precharge times increase because of the increase in capacitance associated with capacitances 112 and 113. Hence, there is a need in the art for a mechanism which improves the read access time by enhancing the rate at which a differential read signal is developed on a pair of bitlines, on a memory bitline column.